FIELD OF THE INVENTION
This invention relates to a method of fabricating a field emission display (FED) device having a silicon tip, and more particularly to a method of fabricating a FED device which can reduce manufacturing process and increase the electron emission efficiency of a silicon tip which is formed by etching a silicon substrate using a photoresist pattern as an mask.
In the application field of vacuum microelectronics, it is noted that a flat display is currently being actively studied. A field emission display device has a silicon tip or a metal tip.
A conventional FED having a silicon tip will be explained with reference to FIGS. 1A through 1I. As shown in FIG. 1A, a thermal oxide (or nitride) film 2 is formed on a silicon substrate 1. A photoresist pattern 3 is formed on the thermal oxide film 2, as shown in FIG. 1B. Referring to FIG. 1C, the thermal oxide film 2 exposed to the photoresist pattern 3 is etched and the photoresist pattern 3 is then removed, as shown in FIG. 1D. In the next process, as shown in FIG. 1E, an anisotropic etching process is performed to etch the silicon substrate 1 using the thermal oxide film 2 as a mask. Referring to FIG. 1F, an insulation layer 4 such as an oxide film of which stepcoverage is poor, for example an electron beam deposition oxide film, is formed on the thermal oxide film 2 and the silicon substrate 1. A thermal oxidation process is performed to form a sharp silicon tip, whereby a second thermal oxide film 6 is formed on the surface of the silicon substrate, as shown in FIG. 1G. By performing the thermal oxidation process, the second thermal oxide film 6 is formed with the ratio of Si:SiO.sub.2 =45:55. A metal deposition process is performed so that a gate metal layer 5 is formed on the oxide film 4, as shown in FIG. 1H. The wet etching process is performed to form a silicon tip 7, as shown in FIG. 1I.
As described above, since the conventional method has a plurality of fabrication steps, manufacturing costs become high. Also, there is a problem in that the electron emission efficiency is decreased and the properties of the device lowered since the gap between the silicon tip 7 and the gate metal layer 5 is wide.